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The PoC-Library Documentation

PoC - “Pile of Cores” provides implementations for often required hardware functions such as Arithmetic Units, Caches, Clock-Domain-Crossing Circuits, FIFOs, RAM wrappers, and I/O Controllers. The hardware modules are typically provided as VHDL or Verilog source code, so it can be easily re-used in a variety of hardware designs.

All hardware modules use a common set of VHDL packages to share new VHDL types, sub-programs and constants. Additionally, a set of simulation helper packages eases the writing of testbenches. Because PoC hosts a huge amount of IP cores, all cores are grouped into sub-namespaces to build a better hierachy.

Various simulation and synthesis tool chains are supported to interoperate with PoC. To generalize all supported free and commercial vendor tool chains, PoC is shipped with a Python based infrastructure to offer a command line based frontend.

News

Attention

In Feb. 2025, The PoC-Library was forked to the VHDL namespace at GitHub, which is operated by the Open-Source VHDL Group (OSVG). It’s planned to update The PoC-Library (new features, bug fixes, etc) as well as removing some burdens like Xilinx ISE support.

In July 2025, the changes made, upcoming changes as well as a roadmap will be presented at FPGA Conference Europe 2025 in Munich. Besides general PoC updates, a first AXI4-Lite IP core will be release to The PoC-Library.

See Change Log for latest updates.

Cite the PoC-Library

The PoC-Library hosted at GitHub.com. Please use the following biblatex entry to cite us:

# BibLaTex example entry
@online{poc,
  title={{PoC - Pile of Cores}},
  author={{Contributors of the Open Source VHDL Group}},
  organization={{OSVG}},
  year={2025},
  url={https://github.com/VHDL/PoC},
  urldate={2025-03-04},
}